Complex modern data processing systems now often use two or more processors together with a large number of peripheral or I/O devices which are accessible from one or more of the processors through control units or interfaces. Modern system organization increasingly uses hierarchal structures in which two or more central processors (CPUs) transfer data to and from a plurality of I/O devices through control units (CUs) having specific capabilities. Characteristically, the CU monitors the states of the I/O devices while also interchanging acknowledgement sequences with both the CPUs and the I/O devices, and further enables a CPU to acquire control of, and transfer data with, a given I/O device. In this type of arrangement, the CU performs not only multiplexing functions but also carries out internal monitoring sequences so as to provide the CPU with current indications as to the availability of the I/O devices and their status when performing given tasks.
Usually, the CPUs function in a master-slave relationship with the CUs, in that the CUs are held subservient to commands and requests, and required to respond when queried. Although the control unit may seek to complete a scan of the coupled I/O devices, and to undertake internal signal sequencing so as to complete various functions, it cannot independently delay responses to requests for status from the CPUs. Thus when a control unit is required to respond to two asynchronous CPUs, it may do so on a priority basis but must interrupt its current activity in order to effect the response, then go back to the appropriate cycle point. However, the control unit may be coupled to processors having significantly differing data rates, such as a large central processor which cooperates with and also operates independently of a smaller satellite processor, with both seeking access to the same I/O devices. The higher speed processor establishes a queue of initiatives which it may seek to undertake, and may go through this queue very rapidly and return with a given status request to a particular control unit which is seeking to undertake other action. If the control unit, for example, is seeking to reconnect to the slower speed processor, then it must ascertain that a given I/O device has completed a previously assigned task and is available for the next step in the processor program, and then an attempt must be made to gain reconnection attention to the slower speed processor. However, before the reconnection can be established the higher speed processor may initiate a status request, requiring a response before the control unit sequence has been completed. When the I/O device to which the higher speed processor is seeking access is the same one that was previously connected with the slower speed processor, and for which the reconnection must be established, repeated requests for status by the higher speed processor will only derive the indication that the particular device is busy, thus establishing the impasse condition. It is not desirable to redesign control units so as to operate with sufficient independence to assure that the impasse cannot arise because this would adversely affect the hierarchy of control. It is also not desirable to impose added software requirements on the central processor systems.